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Models for Full-Chip Power Dissipation in Field Programmable Gate Arrays and the Impact of Subthreshold Leakage Current.
Arifur Rahman
Published in:
VLSI (2003)
Keyphrases
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power dissipation
digital signal processing
programmable logic
low power
high density
field programmable gate array
computer vision
power consumption
image processing algorithms
parallel computing
cmos technology
chip design