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A floorplan-aware high-level synthesis algorithm for multiplexer reduction targeting FPGA designs.
Koichi Fujiwara
Shin-ya Abe
Kazushi Kawamura
Masao Yanagisawa
Nozomu Togawa
Published in:
APCCAS (2014)
Keyphrases
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learning algorithm
np hard
detection algorithm
preprocessing
dynamic programming
parallel implementation
parallel architecture
optimal solution
k means
probabilistic model
worst case
hardware implementation
computational complexity
high speed
high level synthesis