Impact of random telegraph noise on CMOS logic circuit reliability.
Takashi MatsumotoKazutoshi KobayashiHidetoshi OnoderaPublished in: CICC (2014)
Keyphrases
- delay insensitive
- chip design
- circuit design
- high speed
- analog vlsi
- digital circuits
- asynchronous circuits
- logic synthesis
- low power
- logic circuits
- cmos technology
- low voltage
- noise level
- noisy data
- noise model
- power dissipation
- random noise
- signal to noise ratio
- missing data
- flip flops
- micron cmos
- power consumption
- logic programming
- modal logic
- vlsi circuits
- real time
- power supply
- classical logic
- gaussian noise
- noise reduction
- logic programs
- low cost