A 3D Tiled Low Power Accelerator for Convolutional Neural Network.
Yuxiang HuanJiawei XuLirong ZhengHannu TenhunenZhuo ZouPublished in: ISCAS (2018)
Keyphrases
- low power
- convolutional neural network
- power consumption
- low cost
- high speed
- face detection
- high power
- parallel implementation
- neural network
- wireless transmission
- single chip
- low power consumption
- vlsi architecture
- vlsi circuits
- logic circuits
- digital signal processing
- image sensor
- gate array
- delay insensitive
- power reduction
- field programmable gate array
- object detection
- mixed signal
- general purpose