Scaling of analog LDPC decoders in sub-100 nm CMOS processes.
Meysam ZarghamChristian SchlegelJorge Pérez ChamorroCyril LahuecFabrice SeguinMichel JézéquelVincent C. GaudetPublished in: Integr. (2010)
Keyphrases
- analog vlsi
- circuit design
- low power
- decoding algorithm
- mixed signal
- power consumption
- high speed
- ldpc codes
- cmos technology
- focal plane
- low cost
- silicon on insulator
- low density parity check
- metal oxide semiconductor
- image sensor
- low complexity
- image quality
- image compression
- delay insensitive
- floating gate
- cmos image sensor
- nm technology