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A slew-rate controlled output driver using PLL as compensation circuit.
Soon-Kyun Shin
Seok-Min Jung
Jin-Ho Seo
Myeong-Lyong Ko
Jae-Whui Kim
Published in:
IEEE J. Solid State Circuits (2003)
Keyphrases
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high speed
steady state
circuit design
multiple input
analog vlsi
duty cycle
data sets
artificial intelligence
information systems
image processing
video sequences
false positives
dangerous situations