Reconfigurable Low Power Architecture for Fault Tolerant Pseudo-Random number Generation.
Nemanja SavicMile K. StojcevTatjana R. NikolicVladimir PetrovicGoran S. JovanovicPublished in: J. Circuits Syst. Comput. (2014)
Keyphrases
- fault tolerant
- low power
- low cost
- vlsi architecture
- fault tolerance
- pseudo random number
- power consumption
- high speed
- cmos technology
- distributed systems
- interconnection networks
- mixed signal
- power reduction
- logic circuits
- single chip
- load balancing
- vlsi circuits
- random numbers
- nm technology
- real time
- digital signal processing
- signal processor
- low power consumption
- data flow