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Reconfigurable Low Power Architecture for Fault Tolerant Pseudo-Random number Generation.
Nemanja Savic
Mile K. Stojcev
Tatjana R. Nikolic
Vladimir Petrovic
Goran S. Jovanovic
Published in:
J. Circuits Syst. Comput. (2014)
Keyphrases
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fault tolerant
low power
low cost
vlsi architecture
fault tolerance
pseudo random number
power consumption
high speed
cmos technology
distributed systems
interconnection networks
mixed signal
power reduction
logic circuits
single chip
load balancing
vlsi circuits
random numbers
nm technology
real time
digital signal processing
signal processor
low power consumption
data flow