A 86 MHz-12 GHz Digital-Intensive PLL for Software-Defined Radios, Using a 6 fJ/Step TDC in 40 nm Digital CMOS.
Jonathan BorremansKameswaran VengattaramaneVito GianniniBjörn DebaillieWim Van ThilloJan CraninckxPublished in: IEEE J. Solid State Circuits (2010)