A High-Speed/Low-Power Multiplier Using an Advanced Spurious Power Suppression Technique.
Kuan-Hung ChenYuan-Sun ChuYu-Min ChenJiun-In GuoPublished in: ISCAS (2007)
Keyphrases
- low power
- high speed
- power consumption
- high power
- power reduction
- low cost
- energy dissipation
- vlsi architecture
- single chip
- power management
- wireless transmission
- power dissipation
- digital signal processing
- cmos technology
- power saving
- floating point
- energy efficiency
- low power consumption
- edge detection
- gate array
- ultra low power
- vlsi circuits
- logic circuits
- computational power
- image processing
- delay insensitive
- signal processor
- real time