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Modelling and mitigation of time-zero variability in sub-16nm finfet-based STT-MRAM memories.

Matthias HartmannHalil KüknerPrashant AgrawalPraveen RaghavanLiesbet Van der PerreWim Dehaene
Published in: ACM Great Lakes Symposium on VLSI (2014)
Keyphrases
  • design considerations
  • neural network
  • real world
  • database
  • real time
  • genetic algorithm
  • software engineering
  • information processing
  • software product line
  • random access memory
  • content addressable