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Soft-Error-Aware Read-Stability-Enhanced Low-Power 12T SRAM With Multi-Node Upset Recoverability for Aerospace Applications.
Soumitra Pal
Wing-Hung Ki
Chi-Ying Tsui
Published in:
IEEE Trans. Circuits Syst. I Regul. Pap. (2022)
Keyphrases
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low power
power consumption
low cost
high speed
single chip
digital signal processing
wireless transmission
high power
cmos technology
vlsi architecture
power management
power saving
low power consumption
power reduction
logic circuits
error correction
signal processor
gate array