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Double Precision Sparse Matrix Vector Multiplication Accelerator on FPGA.
Sumedh Attarde
Siddharth Joshi
Yash Deshpande
Sunil Puranik
Sachin B. Patkar
Published in:
PECCS (2011)
Keyphrases
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sparse matrix
field programmable gate array
floating point
sparse linear
hardware implementation
parallel computing
embedded systems
signal processing
random projections
parallel implementation
multi objective