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Partial Reconfiguration of Flux Limiter Functions in MUSCL Scheme Using FPGA.
Mohamad Sofian Abu Talip
Takayuki Akamine
Yasunori Osana
Naoyuki Fujita
Hideharu Amano
Published in:
IEICE Trans. Inf. Syst. (2012)
Keyphrases
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high speed
neural network
database
computer vision
data acquisition
hardware implementation
classification scheme
fpga implementation
information systems
image quality
single chip
parallel architecture
hardware architectures