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Retiming of synchronous circuits with variable topology.

Sven SimonRalf BucherJosef A. Nossek
Published in: VLSI Design (1995)
Keyphrases
  • high speed
  • circuit design
  • cell complexes
  • information retrieval
  • digital circuits
  • asynchronous communication
  • delay insensitive
  • vlsi circuits
  • learning algorithm
  • analog circuits
  • electronic circuits
  • analog vlsi