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24.2 A 2.5GHz 7.7TOPS/W switched-capacitor matrix multiplier with co-designed local memory in 40nm.
Edward H. Lee
S. Simon Wong
Published in:
ISSCC (2016)
Keyphrases
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memory requirements
memory usage
linear algebra
power supply
associative memory
data sets
neural network
high speed
low rank
limited memory
short circuit