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A 4.5mW/Gb/s 6.4Gb/s 22+1-lane source-synchronous link rx core with optional cleanup PLL in 65nm CMOS.
Robert Reutemann
Michael Ruegg
Fran Keyser
John Bergkvist
Daniel Dreps
Thomas Toifl
Martin L. Schmatz
Published in:
ISSCC (2010)
Keyphrases
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high speed
power consumption
power supply
low power
link structure
hd video
nm technology
analog vlsi