Stretching the limits of FPGA SerDes for enhanced ATE performance.

A. M. Majid David C. Keezer

Published in: DATE (2010)

Keyphrases

high speed
hardware implementation
hardware architecture
real time
neural network
signal processing
real time image processing
hardware architectures
verilog hdl
artificial intelligence
low cost
field programmable gate array
fpga implementation
parallel hardware
systolic array