A Design of 44.1 fJ/Conv-Step 12-Bit 80 ms/s Time Interleaved Hybrid Type SAR ADC With Redundancy Capacitor and On-Chip Time-Skew Calibration.
Deeksha VermaBehnam Samadpoor RikanKhuram ShehzadSung Jin KimDanial KhanVenkatesh KommanguntaSyed Adil Ali ShahYoungGun PuSang-Sun YooKeum-Cheol HwangYoungoo YangKang-Yoon LeePublished in: IEEE Access (2021)