Useful-Skew Clock Routing With Gate Sizing for Low Power Design.
Joe G. XiWayne Wei-Ming DaiPublished in: DAC (1996)
Keyphrases
- low power
- power consumption
- high speed
- cmos technology
- low cost
- single chip
- low power consumption
- vlsi architecture
- nm technology
- digital signal processing
- logic circuits
- gate array
- power dissipation
- design process
- vlsi circuits
- ultra low power
- real time
- power reduction
- signal processing
- mixed signal
- wireless transmission
- high power
- low voltage
- hardware and software
- parallel processing