Login / Signup

A 90nm 8×16 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations.

Yuuri SugiharaManabu KotaniKazuya KatsukiKazutoshi KobayashiHidetoshi Onodera
Published in: ASP-DAC (2007)
Keyphrases
  • high speed
  • real time
  • real time image processing
  • view angle
  • signal processing
  • decision trees
  • general purpose
  • low power
  • hardware implementation
  • processing speed
  • field programmable gate array
  • low power consumption