Low Power SER Tolerant Design to Mitigate Single Event Transients in Nanoscale Circuits.
Praveen ElakkumananKishan PrasadRamalingam SridharPublished in: J. Low Power Electron. (2005)
Keyphrases
- low power
- logic circuits
- high speed
- cmos technology
- power dissipation
- mixed signal
- single chip
- power reduction
- power consumption
- low power consumption
- low cost
- vlsi circuits
- vlsi architecture
- delay insensitive
- digital signal processing
- low voltage
- multi channel
- high power
- gate array
- real time
- digital circuits
- embedded systems
- design process
- nm technology
- ultra low power