A Low-Power and Low-Noise 20: 1 Serializer with Two Calibration Loops in 55-nm CMOS.
Yong-Un JeongJoo-Hyung ChaeSungphil ChoiJaekwang YunShin-Hyun JeongSuhwan KimPublished in: ISLPED (2019)
Keyphrases
- low power
- cmos technology
- power consumption
- low cost
- nm technology
- high speed
- low power consumption
- high power
- vlsi circuits
- single chip
- energy dissipation
- image sensor
- ultra low power
- low voltage
- power reduction
- logic circuits
- wireless transmission
- digital signal processing
- vlsi architecture
- power dissipation
- signal to noise ratio
- delay insensitive
- power management
- mixed signal
- noise model
- wide dynamic range
- image processing