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A Heuristic for Clock Selection in High-Level Synthesis.
J. Ramanujam
Sandeep Deshpande
Jinpyo Hong
Mahmut T. Kandemir
Published in:
VLSI Design (2002)
Keyphrases
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high level synthesis
search algorithm
optimal solution
selection strategies
parallel architecture
image processing
real world
pairwise
design space exploration
duty cycle