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Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL.
John G. Maneatis
Jaeha Kim
Iain McClatchie
Jay Maxey
Manjusha Shankaradas
Published in:
IEEE J. Solid State Circuits (2003)
Keyphrases
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high bandwidth
end to end
low latency
application specific
high density
high speed
mobile terminals
general purpose
hardware implementation
real time
parallel architectures