A Fast Macro Based Compilation Methodology for Partially Reconfigurable FPGA Designs.
Manish HandaRajesh RadhakrishnanMadhubanti MukherjeeRanga VemuriPublished in: VLSI Design (2003)
Keyphrases
- field programmable gate array
- hardware implementation
- low cost
- application specific integrated circuits
- systolic array
- general purpose
- high speed
- digital signal
- real time
- parallel architecture
- hardware software co design
- hardware architecture
- hardware design
- reconfigurable architecture
- code generation
- real time image processing
- reconfigurable hardware
- embedded systems
- data acquisition
- data sets