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A 600MS/s 30mW 0.13µm CMOS ADC array achieving over 60dB SFDR with adaptive digital equalization.
Wenbo Liu
Yuchun Chang
Szukang Hsien
Bo-Wei Chen
Yung-Pin Lee
Wen-Tsao Chen
Tzu-Yi Yang
Gin-Kou Ma
Yun Chiu
Published in:
ISSCC (2009)
Keyphrases
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analog to digital converter
power consumption
power supply
circuit design
low power
image sensor
hd video
high speed
sigma delta
charge coupled device
wide dynamic range
cmos image sensor
low cost
mixed signal
single chip
floating gate
random access memory
programmable logic
focal plane
database