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A multipage cell architecture for high-speed programming multilevel NAND flash memories.
Ken Takeuchi
Tomoharu Tanaka
Toru Tanzawa
Published in:
IEEE J. Solid State Circuits (1998)
Keyphrases
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high speed
real time
associative memory
programming language
content addressable
low power
network architecture
management system
hardware implementation
neural network
computer programming
source code
object oriented programming
storage devices
architectural design
high level language
data sets