SRAM- and STT-RAM-based hybrid, shared last-level cache for on-chip CPU-GPU heterogeneous architectures.
Lan GaoRui WangYunlong XuHailong YangZhongzhi LuanDepei QianHan ZhangJihong CaiPublished in: J. Supercomput. (2018)
Keyphrases
- memory access
- random access memory
- memory hierarchy
- multithreading
- memory bandwidth
- heterogeneous computing
- memory management
- data access
- main memory
- cache misses
- parallel computing
- dynamic random access memory
- low cost
- real time
- shared memory
- gpu implementation
- graphics processors
- graphics processing units
- data management
- parallel architectures
- heterogeneous environments
- processing units
- power consumption
- operating system
- high speed
- data structure
- external memory
- design considerations
- parallel computation
- data transfer
- multi core processors
- access patterns
- parallel implementation
- parallel processing
- query processing