A 350-mV, under-200-ppm allan deviation floor gate-leakage-based timer using an amplifier-less replica-bias switching technique in 55-nm DDC CMOS.
Atsuki KobayashiYuya NishioKenya HayashiKazuo NakazatoKiichi NiitsuPublished in: CICC (2018)
Keyphrases
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