Low power dual matchline ternary content addressable memory.

Nitin Mohan Manoj Sachdev

Published in: ISCAS (2) (2004)

Keyphrases

low power
high speed
content addressable memory
low cost
power consumption
vlsi architecture
single chip
digital signal processing
image sensor
cmos technology
real time
logic circuits
low power consumption
vlsi circuits
gate array
power reduction