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A New Automatic Logic Interconnection Verification System for VLSI Design.
Takashi Watanabe
Makoto Endo
Norio Miyahara
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1983)
Keyphrases
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vlsi design
asynchronous circuits
verification method
model checking
design methodology
model checker
database
social networks
case study
data warehouse
logic programming
high density
formal methods
automated reasoning
formal verification