A reconfigurable 10-12b 0.4-44MS/s pipelined ADC with 0.35-0.5pJ/step in 1.2V 90nm digital CMOS.
Mohammad Taherzadeh-SaniAnas A. HamouiPublished in: ESSCIRC (2010)
Keyphrases
- analog to digital converter
- low cost
- metal oxide semiconductor
- circuit design
- post processing
- high speed
- digital images
- silicon on insulator
- cmos image sensor
- general purpose
- low power
- cmos technology
- mixed signal
- power consumption
- sigma delta
- data flow
- vlsi circuits
- delay insensitive
- real time
- multi objective evolutionary
- analog vlsi
- hardware implementation
- digital curves
- image sensor
- dynamic range
- image processing algorithms