A Fault Tolerant Hierarchical Network on Chip Router Architecture.

Mohammad Hossein Neishaburi Zeljko Zilic

Published in: DFT (2011)

Keyphrases

fault tolerant
network on chip
interconnection networks
fault tolerance
multi processor
routing algorithm
packet switched
distributed systems
network simulator
load balancing
data transfer
real time
program execution
power dissipation
mobile devices
message passing