Exploiting Sparse Activation for Low-Power Design of Synchronous Neuromorphic Systems.

Jaeyong Chung Woochul Kang

Published in: IEICE Trans. Electron. (2017)

Keyphrases

low power
single chip
power consumption
low power consumption
low cost
high speed
vlsi architecture
digital signal processing
logic circuits
ultra low power
mixed signal
embedded systems
gate array
cmos technology
power dissipation
power reduction
design process
digital circuits
high power