A Reconfigurable DNN Training Accelerator on FPGA.
Jinming LuJun LinZhongfeng WangPublished in: SiPS (2020)
Keyphrases
- field programmable gate array
- training process
- hardware implementation
- low cost
- parallel computing
- image processing algorithms
- hardware architecture
- digital signal
- embedded systems
- training set
- systolic array
- signal processing
- fpga implementation
- hardware design
- training examples
- supervised learning
- training phase
- computing systems
- training algorithm
- test set
- reconfigurable hardware
- online learning
- reconfigurable architecture
- massively parallel
- parallel architecture
- software implementation
- real time image processing
- hardware software
- training samples
- xilinx virtex
- fpga technology