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A 1.8V 6-bit 1GS/s 60mW CMOS folding/interpolation ADC using folder reduction circuit and auto switching encoder.
Junho Moon
Heewon Kang
Daeyoon Kim
Seungjin Yeo
Dubok Lee
Minkyu Song
Published in:
ICECS (2008)
Keyphrases
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power reduction
power consumption
analog to digital converter
low power
power saving
power dissipation
mixed signal
image sensor
nm technology
single chip
tunnel diode
cmos technology
image interpolation
vlsi circuits
wide dynamic range
high speed
email
power supply
random access memory
hd video
low complexity