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A 10-bit DC-20-GHz Multiple-Return-to-Zero DAC With >48-dB SFDR.
Lucas Duncan
Brian Dupaix
Jamin J. McCue
Brandon Mathieu
Matthew LaRue
Vipul J. Patel
Mesfin Teshome
Myung-Jun Choe
Waleed Khalil
Published in:
IEEE J. Solid State Circuits (2017)
Keyphrases
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real time
data sets
case study
multiscale
high speed
combining multiple