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A 86MHz-to-12GHz digital-intensive phase-modulated fractional-N PLL using a 15pJ/Shot 5ps TDC in 40nm digital CMOS.
Jonathan Borremans
Kameswaran Vengattaramane
Kameswaran Giannini
Jan Craninckx
Published in:
ISSCC (2010)
Keyphrases
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high speed
image processing
low cost
circuit design
real time
digital curves
cmos technology