A Low-Power Double-Edge-Triggered Address Pointer Circuit for FIFO Memory Design.
Saravanan RamamoorthyHaibo WangSarma B. K. VrudhulaPublished in: ISQED (2008)
Keyphrases
- low power
- power dissipation
- high speed
- logic circuits
- power consumption
- gate array
- cmos technology
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- power reduction
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- nm technology
- low power consumption
- vlsi circuits
- vlsi architecture
- digital signal processing
- circuit design
- mixed signal
- delay insensitive
- cmos image sensor
- ultra low power
- real time
- image sensor
- high power
- computational power
- data structure