A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit.
Fumihiko TachibanaOsamu HirabayashiYasuhisa TakeyamaMiyako ShizunoAtsushi KawasumiKeiichi KushidaAzuma SuzukiYusuke NikiShinichi SasakiTomoaki YabeYasuo UnekawaPublished in: IEEE J. Solid State Circuits (2014)
Keyphrases
- power reduction
- power supply
- power consumption
- power dissipation
- low power
- high power
- power saving
- energy supply
- single phase
- energy efficiency
- electrical power
- intelligent control
- high frequency
- energy saving
- data center
- cmos technology
- dc dc converter
- high speed
- artificial neural networks
- rbf neural network
- digital signal processing
- artificial intelligence
- clock gating
- real time