Minimising buffer latency through optimum transistor p-to-n ratio scaling.

Conor Buckley Sverre Lidholm

Published in: ECCTD (2005)

Keyphrases

replacement policy
high speed
buffer management
hit ratio
prefetching
integrated circuit
low latency
real time
low power
response time
standard deviation
web prefetching
access patterns
silicon dioxide
database
global optimum
neural network