A 20.8-23.2GHz sub-sampling PLL with transformer-coupled VCO feedback loop achieving -47.05dBc reference spur and -245.9dB FOM in 40nm CMOS technology.
Zhichao ZhangWenjie ZhengXinlin XiaYanjie WangPublished in: IEICE Electron. Express (2023)
Keyphrases
- cmos technology
- feedback loop
- low power
- power consumption
- high speed
- spl times
- low voltage
- clock frequency
- parallel processing
- steady state
- power dissipation
- mixed signal
- silicon on insulator
- image sensor
- fuzzy logic
- image processing
- frequency band
- fault diagnosis
- low cost
- finite element model
- power management
- digital images
- flip flops