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Decomposing specifications with concurrent outputs to resolve state coding conflicts in asynchronous logic synthesis.

Hemangee K. KapoorMark B. Josephs
Published in: DAC (2004)
Keyphrases
  • logic synthesis
  • delay insensitive
  • resolving conflicts
  • machine learning
  • state space
  • wireless networks
  • boolean functions
  • finite state machines
  • logic circuits