A Shared-Bus Control Mechanism and a Cache Coherence Protocol for a High-Performance On-Chip Multiprocessor.
Masafumi TakahashiHiroyuki TakanoEmi KanekoSeigo SuzukiPublished in: HPCA (1996)
Keyphrases
- high speed
- highly parallel
- distributed memory
- signal processor
- single chip
- low cost
- low power consumption
- lightweight
- database machines
- analog vlsi
- low power
- level parallelism
- multiprocessor systems
- multithreading
- shared memory multiprocessors
- formal analysis
- scheduling algorithm
- signal processing
- vlsi implementation
- programmable logic
- tcp ip
- communication protocol
- high density
- parallel implementation
- physical design
- authentication protocol
- real time