Parallel pipelined histogram architecture via C-slow retiming.
José O. CadenasR. Simon SherrattPablo HuertaWen-Chung KaoGraham M. MegsonPublished in: ICCE (2013)
Keyphrases
- parallel architecture
- master slave
- data flow
- management system
- parallel processing
- distributed processing
- parallel implementation
- multi processor
- distributed memory
- database
- shared memory
- network architecture
- software architecture
- multi core processors
- processor array
- distributed architecture
- massively parallel
- hardware implementation
- gray level
- real time
- parallel programming
- processing units
- architectural design
- load balancing
- single processor
- multi agent
- neural network
- level parallelism