The Research and Implementation of Reconfigurable Processor Architecture for Block Cipher Processing.
Zibin DaiWei LiXiaohui YangTao ChenQiao RenPublished in: ICESS (2008)
Keyphrases
- parallel architecture
- hardware implementation
- computation intensive
- reconfigurable hardware
- systolic array
- processing elements
- general purpose processors
- memory management
- low cost
- instruction set
- parallel processing
- functional units
- hardware architecture
- field programmable gate array
- real time
- block cipher
- hardware software
- xilinx virtex
- dynamic reconfiguration
- single instruction multiple data
- parallel computers
- fpga device
- efficient implementation
- distributed memory
- high speed
- shared memory