Certifying Machine Code Safe from Hardware Aliasing: RISC is Not Necessarily Risky.
Peter T. BreuerJonathan P. BowenPublished in: SEFM Workshops (2013)
Keyphrases
- hardware architecture
- instruction set
- real time
- low power consumption
- low cost
- hardware and software
- hardware implementation
- error detection
- digital computer
- protection scheme
- high frequency
- application specific
- hardware description language
- source code
- super resolution
- frequency domain
- digital images
- high resolution
- java virtual machine
- spatial resolution
- vlsi implementation
- hardware design
- computer systems
- processor core
- central processing unit
- data flow
- industry standard
- parallel machines
- reconstruction error
- computing systems
- embedded systems
- multiresolution
- image processing