A 250MHz-to-4GHz Δ-Σ fractional-N frequency synthesizer with adjustable duty cycle.

Chen-Wei Huang Ping Gui

Published in: ISCAS (2010)

Keyphrases

duty cycle
clock frequency
power consumption
high end
parallel computing
massively parallel
parallel architecture
field programmable gate array
cmos technology
low power
signal processing
distributed systems
computer systems
high performance computing
cache misses