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A 1.6 GHz Non-overlap Clock Generation with Differential Clock Driver and Clock Level Shifters for GS/s Sampling Rate Pipeline ADCs.
Hakan Cetinkaya
Ali Zeki
Alper Girgin
Enver Derun Karabeyoglu
Tufan Coskun Karalar
Published in:
ICECS (2018)
Keyphrases
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high speed
power consumption
sampling rate
duty cycle
low power
real time
neural network
genetic algorithm
multiresolution
image data