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A 90 nm FPGA I/O buffer design with 1.6 Gbps data rate for source-synchronous system and 300 MHz clock rate for external memory interface.

Jeffrey TyhachBonnie WangChiakang SungJoseph HuangKhai NguyenXiaobao WangYan ChongPhilip PanHenry KimGopinath RanganTzung-Chin ChangJohnson Tan
Published in: CICC (2004)
Keyphrases
  • high speed
  • external memory
  • data structure
  • image data
  • data sources
  • database
  • memory access
  • main memory
  • memory space
  • data model
  • binary images
  • hardware architecture
  • disk storage